Bitwise

The bitwise part of IR APIs.

tvm.aipu.script.ir.bitwise.vand(x, y, mask=None)

Computes the bit-wise AND on active elements of x with the corresponding elements of y.

• The mask situation where both x and y are mask is also supported.

• The inactive elements of result vector are set to False for mask situation, undefined for others.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     1         2         3         4         5        6         7         8
      00000001  00000010  00000011  00000100  00000101  00000110  00000111  00001000
   y:     5         6         7         8        -9       -10       -11       -12
      00000101  00000110  00000111  00001000  11110111  11110110  11110101  11110100
mask:     T         T         F         T         T        F         T         T

 out = S.vand(x, y, mask)
 out:     1         2         ?         0         5        ?         5         0
      00000001  00000010      ?     00000000  00000101     ?      00000101  00000000

Parameters

x, yUnion[PrimExpr, int]

The operands. If either one is a scalar, it will be automatically broadcast.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”, “bool8/16/32”.

Examples

vc = S.vand(va, vb)
vc = S.vand(va, 3)
vc = S.vand(va, vb, mask="3T5F")
vc = S.vand(va, vb, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vand

tvm.aipu.script.ir.bitwise.vor(x, y, mask=None)

Computes the bit-wise OR on active elements of x with the corresponding elements of y.

• The mask situation where both x and y are mask is also supported.

• The inactive elements of result vector are set to False for mask situation, undefined for others.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     1         2         3         4         5        6         7         8
      00000001  00000010  00000011  00000100  00000101  00000110  00000111  00001000
   y:     5         6         7         8        -9       -10       -11       -12
      00000101  00000110  00000111  00001000  11110111  11110110  11110101  11110100
mask:     T         T         F         T         T        F         T         T

 out = S.vor(x, y, mask)
 out:     5         6         ?        12        -9        ?        -9        -4
      00000101  00000110      ?     00001100  11110111     ?      11110111  11111100

Parameters

x, yUnion[PrimExpr, int]

The operands. If either one is a scalar, it will be automatically broadcast.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”, “bool8/16/32”.

Examples

vc = S.vor(va, vb)
vc = S.vor(va, 3)
vc = S.vor(va, vb, mask="3T5F")
vc = S.vor(va, vb, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vor

tvm.aipu.script.ir.bitwise.vinv(x, mask=None)

Computes the bit-wise inversion or bit-wise NOT on active elements of x.

• The mask situation where x is a mask is also supported.

• The inactive elements of result vector are set to False for mask situation, undefined for others.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     1         2         3         4         5         6         7         8
      00000001  00000010  00000011  00000100  00000101  00000110  00000111  00001000
mask:     T         F         F         T         T         T         T         T

 out = S.vinv(x, mask)
 out:    -2         ?         ?        -5        -6        -7        -8        -9
      11111110      ?         ?     11111011  11111010  11111001  11111000  11110111

Parameters

xPrimExpr

The operand.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”, “bool8/16/32”.

Examples

vr = S.vinv(vx)
vr = S.vinv(vx, mask="3T5F")
vr = S.vinv(vx, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vinv

tvm.aipu.script.ir.bitwise.vall(mask)

Computes the logical AND on each element of mask, test whether all elements are True.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

mask(boolx8): T  T  T  T  F  F  F  F

   out = S.vall(mask)
   out(bool): F

Parameters

maskPrimExpr

The operand.

Returns

retPrimExpr

The result expression.

Supported DType

“bool8/16/32”.

Examples

out = S.vall(mask_var)

See Also

• Zhouyi Compass OpenCL Programming Guide: __vandr

tvm.aipu.script.ir.bitwise.vany(mask)

Computes the logical OR on each element of mask, test whether any element is True.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

mask(boolx8): T  T  T  T  F  F  F  F

   out = S.vany(mask)
   out(bool): T

Parameters

maskPrimExpr

The operand.

Returns

retPrimExpr

The result expression.

Supported DType

“bool8/16/32”.

Examples

out = S.vany(mask_var)

See Also

• Zhouyi Compass OpenCL Programming Guide: __vorr

tvm.aipu.script.ir.bitwise.vxor(x, y, mask=None)

Computes the bit-wise XOR on active elements of x with the corresponding elements of y.

• The mask situation where both x and y are mask is also supported.

• The inactive elements of result vector are set to False for mask situation, undefined for others.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     1         2         3         4        5         6         7         8
      00000001  00000010  00000011  00000100  00000101  00000110  00000111  00001000
   y:     5         6         7         8       -9        -10       -11       -12
      00000101  00000110  00000111  00001000  11110111  11110110  11110101  11110100
mask:     T         T         F         T        T         T         T         T

 out = S.vxor(x, y, mask)
 out:     4         4         ?        12       -14       -16       -14       -4
      00000100  00000100      ?     00001100  11110010  11110000  11110010  11111100

Parameters

x, yUnion[PrimExpr, int]

The operands. If either one is a scalar, it will be automatically broadcast.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”, “bool8/16/32”.

Examples

vc = S.vxor(va, vb)
vc = S.vxor(va, 3)
vc = S.vxor(va, vb, mask="3T5F")
vc = S.vxor(va, vb, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vxor

tvm.aipu.script.ir.bitwise.vnsr(x, shift, mask=None, saturate=False, out_sign=None, with_round=False, to_h=False)

Performs a bit-wise right shift on active elements of x, using the corresponding elements of shift as the shift value, then cast the result to the needed narrower bits data type.

Please note that after casting, the meaningful elements of result vector are still in the original position, i.e., they are stored in intervals, not compactly, the meaningless elements as intervals are set to zero.

• The inactive elements of result vector are set to zero.

• The feature Multiple Width Vector is supported.

    x(i32x8):    -9           46            7        ...      6           95
              11110111     00101110     00000111     ...  00000110     01011111
shift(i32x8):     2            1            1        ...      2           -2
mask(boolx8):     T            T            T        ...      F            T

 out = S.vnsr(x, shift, mask, saturate=True, out_sign="u", with_round=True, to_h=True)
 out(u16x16):     0     0     23     0      4     0  ...      0     0      0     0
              00000000     00010111     00000100          00000000     00000000

Parameters

xPrimExpr

The operand.

shiftUnion[PrimExpr, int]

The shift value. If it is a scalar, it will be automatically broadcast. The negative number will be reinterpreted as an unsigned number.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

saturateOptional[bool]

Whether the result needs to be saturated or not.

out_signOptional[str]

Specify whether the output sign is signed or unsigned. None means same as x, u means unsigned, s means signed.

with_roundOptional[bool]

Whether the result needs to be rounded or not.

to_hOptional[bool]

Whether the output type is short.

Returns

retPrimExpr

The result expression.

Supported DType

“int16/32”, “uint16/32”.

Examples

vc = S.vnsr(va, vb)
vc = S.vnsr(va, 3)
vc = S.vnsr(va, vb, mask="3T5F")
vc = S.vnsr(va, vb, mask=S.tail_mask(n, 8))
vc = S.vnsr(va, vb, saturate=True)
vc = S.vnsr(va, vb, out_sigh='s')
vc = S.vnsr(va, vb, with_round=True)
vc = S.vnsr(va, vb, to_h=True)

See Also

• Zhouyi Compass OpenCL Programming Guide: __vnsrl, __vnsrlr, __vnsrls, __vnsrlsr, __vnsra, __vnsrar, __vnsras, __vnsrasr

tvm.aipu.script.ir.bitwise.vnsrsr(x, shift, mask=None, out_sign=None, to_h=False)

Alias of API “vnsr” with the parameter “saturate” and “with_round” fixed set to True.

tvm.aipu.script.ir.bitwise.vsr(x, shift, mask=None, with_round=False, r=None)

Performs a shift by bit to the right of every element of x. Performs arithmetic shift for signed and logical shift for unsigned.

• The inactive elements of result vector are determined by r.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

    x:    -9         8         7         6         5         4         3         2
       11110111  00001000  00000111  00000110  00000101  00000100  00000011  00000010
shift:     4         3         2         1         0        -1        -2        -3
 mask:     T         T         T         F         T         T         T         T
    z:     0         1         2         3         4         5         6         7

  out = S.vsr(x, shift, mask, r=z)
  out:    -1         1         1         3         5         0         0         0
       11111111  00000001  00000001  00000011  00000101  00000000  00000000  00000000

Parameters

xPrimExpr

The operand.

shiftUnion[PrimExpr, int]

The shift value. If it is a scalar, it will be automatically broadcast. The negative number will be reinterpreted as an unsigned number.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

with_roundOptional[bool]

Whether the result needs to be rounded or not.

rOptional[PrimExpr, int, float]

Provide the value of the inactive elements in result vector. If it is a scalar, it will be automatically broadcast. None means the inactive elements of result vector are undefined.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”.

Examples

vc = S.vsr(va, vb)
vc = S.vsr(va, 3)
vc = S.vsr(va, vb, mask="3T5F")
vc = S.vsr(va, vb, mask=S.tail_mask(n, 8))
vc = S.vsr(va, vb, mask=S.tail_mask(n, 8), r=vb)
vc = S.vsr(va, vb, with_round=True)

See Also

• Zhouyi Compass OpenCL Programming Guide: __vlsr, __vasr, __vlsrr, __vasrr

tvm.aipu.script.ir.bitwise.vsl(x, shift, mask=None, saturate=False, r=None)

Performs a shift by bit to the left of every element of x.

• The inactive elements of result vector are determined by r.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

    x:    -9         8         7         6         5         4         3         2
       11110111  00001000  00000111  00000110  00000101  00000100  00000011  00000010
shift:     4         3         2         1         0        -1        -2        -3
 mask:     T         T         T         T         F         F         T         T
    z:     0         1         2         3         4         5         6         7

  out = S.vsl(x, shift, mask, r=z)
  out:   112        64        28        12         4         5         0         0
       01110000  01000000  00011100  00001100  00000100  00000101  00000000  00000000

Parameters

xPrimExpr

The operand.

shiftUnion[PrimExpr, int]

The shift value. If it is a scalar, it will be automatically broadcast. The negative number will be reinterpreted as an unsigned number.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

saturateOptional[bool]

Whether the result needs to be saturated or not.

rOptional[PrimExpr, int, float]

Provide the value of the inactive elements in result vector. If it is a scalar, it will be automatically broadcast. None means the inactive elements of result vector are undefined.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”.

Examples

vc = S.vsl(va, vb)
vc = S.vsl(va, 3)
vc = S.vsl(va, vb, mask="3T5F")
vc = S.vsl(va, vb, mask=S.tail_mask(n, 8))
vc = S.vsl(va, vb, mask=S.tail_mask(n, 8), saturate=True)
vc = S.vsl(va, vb, mask=S.tail_mask(n, 8), saturate=True, r=vb)

See Also

• Zhouyi Compass OpenCL Programming Guide: __vsasl, __vlsl

tvm.aipu.script.ir.bitwise.vror(x, shift, mask=None)

Performs a bit-wise rotate right shift on active elements of x, using the corresponding elements of shift as the shift value.

• The inactive elements of result vector are undefined.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

    x:     1         2         3        -4        -5         6         7         8
       00000001  00000010  00000011  11111100  11111011  00000110  00000111  00001000
shift:     5         9        -7         8        -9         0         1         2
 mask:     T         T         T         T         T         T         T         F

  out = S.vror(x, shift, mask)
  out:     8         1       -127       -4        -9         6       -125        ?
       00001000  00000001  10000001  11111100  11110111  00000110  10000011      ?

Parameters

xPrimExpr

The operand.

shiftUnion[PrimExpr, int]

The shift value. If it is a scalar, it will be automatically broadcast. The negative number will be reinterpreted as an unsigned number.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”.

Examples

vc = S.vror(va, vb)
vc = S.vror(va, 3)
vc = S.vror(va, vb, mask="3T5F")
vc = S.vror(va, vb, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vror

tvm.aipu.script.ir.bitwise.vcls(x, mask=None, out_sign=None)

Counts leading sign bits on active elements of x. Leading signs mean continuous bits equal to the sign bit from the second higher bit to the lowest bit, excluding the sign bit (the highest bit).

• The inactive elements of result vector are undefined.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     0         1         2         5         8        -1        -2        -8
      00000000  00000001  00000010  00000101  00001000  11111111  11111110  11111000
mask:     T         F         T         T         F         T         F         T

 out = S.vcls(x, mask)
 out:     7         ?         5         4         ?         7         ?         4

Parameters

xPrimExpr

The operand, its data type must be signed.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

out_signOptional[str]

Specify whether the output sign is signed or unsigned. None means same as x, u means unsigned, s means signed.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”.

Examples

vr = S.vcls(vx)
vr = S.vcls(vx, mask="3T5F")
u_vr = S.vcls(vx, mask="3T5F", out_sign="u")
vr = S.vcls(vx, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vcls

tvm.aipu.script.ir.bitwise.clz(x, mask=None)

Counts leading zero bits on active elements of x. Leading zeros mean continuous zeros from the highest bit to the lowest bit. If the highest bit is 1, the result will be 0 (No leading zeros have been found).

• The scalar situation where x is a scalar is also supported.

• The inactive elements of result vector are undefined.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     0         1         2         5         8        -1        -2        -8
      00000000  00000001  00000010  00000101  00001000  11111111  11111110  11111000
mask:     T         F         T         T         F         T         F         T

 out = S.clz(x, mask)
 out:     8         ?         6         5         ?         0         ?         0

Parameters

xPrimExpr

The operand.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”.

Examples

 b = S.clz(3)
vb = S.clz(va)
vb = S.clz(va, mask="3T5F")
vb = S.clz(va, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vclz

tvm.aipu.script.ir.bitwise.vbrevs(x, mask=None)

Performs a binary representation sequance reversal on all active elements in vector x.

• The inactive elements of result vector are undefined.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     0         1         2        5          8        -1       -2         -8
      00000000  00000001  00000010  00000101  00001000  11111111  11111110  11111000
mask:     F         T         T        T          T         T        T          T

 out = S.vbrevs(x, mask)
 out:     ?       -128       64       -96        16        -1       127        31
          ?     10000000  01000000  10100000  00010000  11111111  01111111  00011111

Parameters

xPrimExpr

The operand.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”.

Examples

vc = S.vbrevs(va)
vc = S.vbrevs(va, mask="3T5F")
vc = S.vbrevs(va, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vbrevs

tvm.aipu.script.ir.bitwise.vpcnt(x, mask=None, out_sign=None)

Counts non-zero bits on active elements of x.

• The inactive elements of result vector are undefined.

• The feature Flexible Width Vector is supported.

• The feature Multiple Width Vector is supported.

   x:     0         1         2         3         4         5         6         7
      00000000  00000001  00000010  00000011  00000100  00000101  00000110  00000111
mask:     T         F         T         T         F         T         F         T

 out = S.vpcnt(x, mask)
 out:     0         ?         1         2         ?         2         ?         3

Parameters

xPrimExpr

The operand.

maskOptional[Union[Tuple[bool], List[bool], numpy.ndarray[bool], str, PrimExpr]]

The predication mask to indicate which elements of the vector are active for the operation. None means all elements are active.

out_signOptional[str]

Specify whether the output sign is signed or unsigned. None means same as x, u means unsigned, s means signed.

Returns

retPrimExpr

The result expression.

Supported DType

“int8/16/32”, “uint8/16/32”.

Examples

vr = S.vpcnt(vx)
vr = S.vpcnt(vx, mask="3T5F")
u_vr = S.vpcnt(vx, mask="3T5F", out_sign="u")
vr = S.vpcnt(vx, mask=S.tail_mask(n, 8))

See Also

• Zhouyi Compass OpenCL Programming Guide: __vpcnt